Digital display screens are in common use in a wide variety of products, from flat screen televisions and laptop/computer displays to portable personal devices (e.g., mobile phones and music appliances) and from kitchen appliances to automobiles. There are of course other implementations in commercial products which are not for the general retail consumer such as military hardware for which these teachings are equally adaptable. Such display screens are formed of a grid of pixels, each of which changes color and/or greyscale shading by driving a voltage to a certain liquid crystal LC element which is the pixel seen by the human eye. Every pixel of the grid is refreshed at a rate faster than the human eye can detect, typically 60 Hz, to assure the human viewer sees fluid rather than staggered motion of the objects being displayed.
Static displays are not overly demanding on such liquid crystal displays LCDs and the software/hardware processes that control the LCD, but video tends to push the limits of displaying fluid motion, particularly for high resolution LCDs and/or large-screen LCDs. One reason is that conventionally there is one pixel of the grid updated at a time, and so increasing resolution by adding more lines/columns of pixels begins to run up against the 60 Hz screen refresh rate which many manufacturers consider the minimum allowable for good quality video perception. Each pixel must be given some minimum time to change to its new color/shade before the controlling software/hardware moves to update the next pixel of the grid, but the refresh rate for the grid as a whole cannot fall below the 60 Hz limit. This minimum time is termed a gate selection time, since the control line which opens and closes a switch (transistor) for adjusting voltage to a given pixel is termed the pixel's gate (see FIG. 1). For this reason it is sometimes difficult to provide LCDs with the increased resolution (and/or larger screen size) which users often prefer while still retaining the capacity to provide smoothly fluid video which many users have come to take for granted in smaller and less pixellated LCD grids.
One way to avoid the 60 Hz limit is to add a memory element to each pixel; this is termed a memory-in-pixel (MIP) display panel, and a simple circuit diagram of an MIP pixel cell 100 is presented at FIG. 1. MIP enables the refresh rate to be dropped significantly, by example to 10 Hz. This is practical because pixel updating is different with MIP than with ‘normal’ non-MIP processing. Traditionally, MIP technology was developed to reduce power consumption; each pixel having its own memory enables the per-pixel refreshing to be done less often. While refreshing pixels at 10 Hz could cause flicker in the visual display, the flicker potential is offset because pixel luminance does not vary too much when MIP is used. Additionally the MIP display mode for power saving is often designed to use ambient light reflected from the display pixel and flicker is less noticeable in low light. Since sometimes an MIP LCD can operate with or without the MIPs being utilized, many MIP displays can operate in two different modes: normal (non-MIP) mode and MIP mode. In the normal mode the pixel information is refreshed from a display driver integrated circuit IC, and this pixel information always includes full color information. For the 16 million color palette often employed for personal computer and smartphone display screens this means updating 24 bits per pixel. In the MIP mode the pixel information is refreshed from the memory which is on the pixel itself (the MIP) and so the update information can be reduced, by example to 8 colors or 3 bits at low refresh rate to save power.
At FIG. 1 the data source line 101 carries the voltage which gives the pixel its color/shade, and the gate line 102 controls a switch (transistor) 103 whether the data source line 101 is connected or not. The transistor 103 controlled by the gate line 102 is closed during the gate selection time for the FIG. 1 pixel cell 100 and open at all other times (when other pixel cells are being updated) until the refresh rate has cycled through and this pixel cell is again updated. While the gate transistor 103 is closed the liquid crystal element LC 104 is refreshed directly from the data source line 101. The data source line 101 and gate line 102 are conventionally present in both MIP and non-MIP displays. For MIP displays there are additional control lines 106 for operating a memory element 105 (such as for example a 1-bit static random access memory SRAM). The MIP control line 106 controls a switch 107 which when closed allows the data stored in the MIP 105 to refresh the LC 104. The data source line 101, gate line 102 and MIP control line 106 also control other pixel cells and so the various signals/voltages on them are synchronized to select a specific pixel cell at any given time. While FIG. 1 is a simplified circuit and different manufacturers may implement a MIP pixel differently, there is always a source or data line and a gate line controlling whether the source/data line is connected to the pixel being updated, and some control for selecting whether the LC is refreshing from the source line (normal mode) or from the on-cell memory (MIP mode).
FIGS. 2-3 provide a broad overview of how pixel updating works in the different modes. FIG. 2 represents the normal mode in which the MIP functionality is turned off. The information on the source line 101, termed the image information, is updated from a memory 201 of the display driver IC 202 on the display panel 203, and the MIP is not used at all. As in the above example, this is a 24 bit update. At FIG. 3 the MIP functionality is turned on; at step 1 the image information is loaded from the memory 301 of the display driver IC 302 onto the MIP of the display 303 once and then stopped before the next refreshed image frame, and at step 2 the image information is refreshed in the MIP. Timing for this two-step update is done on the display driver IC.
FIG. 4 illustrates what is termed an overshoot/undershoot method for improving the smoothness of moving images displayed on an LCD. The improvement arises by improving the liquid crystal material response time by purposely overshooting the desired voltage (if voltage is increased) or similarly undershooting the desired voltage (if voltage is decreased) to the pixel being updated. There are two phases: first, overshoot (to Vmax at the left side of FIG. 4) or undershoot (to below V0 at the right side of FIG. 4) with a source value, which depends on the previous and the next pixel voltage values and on a constant gate selection time. Next, assert the final value (V0) within the constant gate selection time, where the final value is the desired pixel source value.
As noted above, the gate selection time cannot be changed: too long and the LCD refresh rate is no longer smooth to the human eye, and too short and not all pixels can be updated within one refresh cycle of the given refresh rate. So gate times of phases 1 and 2 also cannot be reduced, because these times depend on the liquid crystal material of the pixel itself. Active source voltage level driving is needed for a minimum time which is dictated by the LC material itself, and this limits the number of lines on the display panel. The next gate cannot yet be selected or else the pixel which that next gate controls will be driven by a voltage for the current gate.
The overdrive/underdrive approach depicted by FIG. 4 is sometimes referred to as a direct driving method. It limits the number of the scanned gate lines what can be implemented on a display panel as follows. Assume each pixel needs 50 μs for driving; this means that only one of the gate lines can be selected during 50 μs when the rest of the gate lines cannot be selected (49 μs to overdrive/underdrive and 1 μs to final drive). The desired refresh rate is 60 Hz (16.6 ms) on the display panel. This means that the maximum number gate lines that can be implemented and driven on the display panel, is 332 lines (=16.6 ms/50 μs). As above, the 50 μs arises from the response time of the LC pixel material itself, so reducing that gate selection time would reduce sharpness of the displayed video by effectively preventing the pixel from achieving its final color.
What is needed in the art is a way to refresh pixels such that an LCD with a very high pixel count can be refreshed fast enough to display to the human eye smooth motion of objects in video while maintaining a wide array of colors for sharpness. Such very high pixel counts may arise from a large screen size and/or high resolution, each of which has additional (vertical and/or horizontal) lines of pixels.